Integrated circuits are fabricated by a series of successive exposure steps with projection in each case of structure patterns arranged on masks into a resist arranged on a substrate. In this case, it is endeavored to form structure patterns on the substrate whose structure elements have the smallest possible lateral dimensions in order, for example, to shorten the timing clock cycles of the integrated circuits with the aim of improving performance and in order to achieve a larger number of circuits per basic area with the aim of saving costs.
However, a lower resolution limit is imposed on the lateral dimensions due to the wavelength of the light used during the lithographic projection and also due to the numerical aperture of the exposure system. Integrated circuits having a high packing density, such as memory products, for instance, are therefore fabricated with lateral dimensions just above this resolution limit.
In this case, the problem arises that, on account of proximity effects, although the structure elements are transferred to the substrate from a mask, the lateral dimensions, respectively, achieved are not reproduced dimensionally accurately on the substrate. One reason for these proximity effects is to be found in lens imperfections, for example. However, a varying resist thickness or a varying topography on the semiconductor substrates may also cause these effects. In addition, so-called micro-loading on account of interactions between chemically active regions, light scattering and reflections are also taken into consideration as causes.
The proximity effects are manifested, for example, in a shortening of the ends of long narrow lines (line shortening), a rounding of line corners envisaged as rectangular in the design, or a narrowing or widening of narrow lines.
One solution to the problem is to compensate for the action of the optical proximity effects by taking account of biases in the design data, i.e., the circuit plans. Such a method is known by the term Optical Proximity Correction (OPC). The biases are set up in such a way that, under the influence of the proximity effects during the projection step, the structure pattern originally provided in the electronically stored circuit layout is actually produced on the substrate.
Higher positional accuracies of, for example, two metal planes, which are patterned one above the other and make contact with one another, are thus achieved with the aid of the OPC method, thereby ensuring a reliable functionality of the integrated circuit to be produced.
Circuit plans are usually present in easily transferable electronic data formats, for example, the GDS II format. In this case, the structure elements stored therein are subdivided hierarchically in planes corresponding to the structure patterns to be formed on the masks. Only a circuit layout comprising a plurality of planes defines the complete integrated circuit. The circuit plans present in such a data format comprise an assignment of structure elements to absolute or relative position coordinates.
The position coordinates are specified in a coordinate grid with a minimum grid size. A smaller grid size, i.e., a narrower coordinate grid enables a higher resolution of structures in the circuit plans. On account of the increasing number of possible grid points, the complexity for the memory space also increases. In particular, the computational complexity for carrying out the OPC method also increases. Data handling, transmission and error checking, etc. thus reach a critical limit.
OPC design software used at the present time attains a data volume up to an order of magnitude of 1 terabyte. Consequently, there is a narrow leeway between the data accuracy to be obtained and feasible technical complexity for carrying out the optical proximity correction.